This invention concerns write bias generators for column multiplexed static random access memories (SRAM). Often the logical layout of SRAM's is not optimum for performance. Where the number of words greatly exceeds the number of bits per word, the layout becomes a thin rectangle. This results in very long column lines. These long column lines have a large capacitance compared with shorter lines, thus requiring more power to drive. Minimization of both the word lines and the column lines requires a more compact layout. This more compact layout is typically achieved using column multiplexing. In column multiplexing, the wordlines enable corresponding rows including plural columns, however, only some of the column bitlines are used. The bitline selection is made via one or more of the address lines.
Memory cells with single ended write ports have an inherent problem when used in a column multiplexed layout. During writes an entire row of memory cells are enabled. Only a single column bitline should be active in order to select the proper memory cell. All the other column bitlines must be left floating. The column bitlines have a capacitance that may store a charge from previous writes. Depending on the conditions, this prior charge may accidentally overwrite memory cells 10 in an unselected column. It is known in the art to bias all the column bitlines to a safe voltage to prevent the memory cells of the unselected columns from being written to due to charge left on the bitline. A bias generator supplies a safe voltage to a corresponding column bitline. This voltage is preferably in the region between the two switching thresholds of the memory cell.